机读格式显示(MARC)

• 000 01350nam2 2200373 4500

• 000 1000008714

• 001 0000164982

• 003 CAL

• 005 20051212163832.0

• 008 040621r20042003cc a b 001 0 eng d

• 017 __ |a 图字：01-2003-7706

• 020 __ |a 7505396641 |c CNY89.00

• 040 __ |a TJU |c XAIT

• 050 _4 |a TK7868.D5 |b .C48 2003

• 082 04 |a 621.39/5 |2 21

• 090 __ |a TP312VH/1E

• 093 __ |a TP312VH |2 4

• 099 __ |a CAL 022004065184

• 100 1_ |a Ciletti, Michael D.

• 245 10 |a Advanced digital design with the Verilog HDL = |b Verilog HDL高级数字设计 / |c Michael D. Ciletti著.

• 246 31 |a Verilog HDL高级数字设计

• 260 __ |a Beijing : |b Publishing House of Electronics Industry, |c 2004.

• 300 __ |a 19, 986 p. : |b ill. ; |c 24 cm.

• 440 _0 |a 国外电子与通信教材系列

• 504 __ |a Includes bibliographical references and index.

• 534 __ |p Reprint. Originally published: |c Upper Saddle River : Prentice Hall, c2003 |z 0130891614.

• 650 _0 |a Logic circuits |x Computer-aided design.

• 650 _0 |a Verilog (Computer hardware description language)

• 650 _0 |a Digital electronics.

• 905 __ |a XATU |d TP312VH/1E

• 920 __ |a 261060 |z 1

• 950 __ |a 261060 |f TP312VH/1

• 991 __022005004648

• 999 __ |t C |A shenxiaoyan |a 20051212 15:05:59 |M shenxiaoyan |m 20051212 15:06:58 |I zhouwei |i 20051212 16:38:32 |G zhouwei |g 20051212 16:38:4