机读格式显示(MARC)

• 000 00972nam a2200289 a 4500

• 001 0000382390

• 003 CAL

• 005 20200723155700.0

• 008 200410s2019 cc a b 000 0 eng d

• 020 __ |a 9787302539278 |c CNY69.80

• 040 __ |a BUA |c BUA

• 090 __ |a TN702.2/E1

• 093 __ |a TN702.2 |2 5

• 099 __ |a CAL 022020012285

• 245 00 |a EDA technology and Verilog HDL / |c Jiye Huang, Xing Zheng, Xiwei Huang, Song Pan = EDA技术与Verilog HDL / 黄继业, 郑兴, 黄汐威, 潘松 编著.

• 260 __ |a 北京 : |b 清华大学出版社, |c 2019.

• 300 __ |a xii, 360 pages. : |b ill. ; |c 26 cm.

• 490 0_ |a 高等院校电子信息科学与工程规划教材

• 504 __ |a Includes bibliographical references.

• 650 _0 |a Integrated circuits |x Computer-aided design.

• 650 _0 |a Verilog (Computer hardware description language)

• 700 1_ |a Huang, Jiye |9 (黄继业)

• 700 1_ |a Zheng, Xing |9 (郑兴)

• 700 1_ |a Huang, Xiwei |9 (黄汐威)

• 700 1_ |a Pan, Song |9 (潘松)

• 920 __ |a 261060 |z 1

• 998 __ |a BUA